Many electrical circuits operate on digital data since there are known advantages to using digital circuit devices. However, some applications require that the output of the digital circuits be converted to the analog domain so that the output can be perceived more easily by humans as well as other entities that are more adapted to receiving and interpreting analog signals than digital signals. Thus, there remains a need to convert digital data into an analog output, for example for audio devices, video devices, and other devices for which an analog signal is advantageous.
The efficient and accurate conversion of digital signals to analog signals, especially at high data rates, continues to be prone to a number of problems, such as performance degradation due to unmatched rise/fall times of the output analog signal, clock jitter limitations, intersymbol interference, and relatively high harmonic distortion, to name a few. Additionally, current digital-to-analog (“DAC”) converters sometimes employ multi-bit truncation DACs, which require Dynamic Element Matching schemes to suppress static nonlinearity conversion errors.
Traditionally, a DAC can be implemented in either discrete time or in continuous time, each with its own drawbacks. For example, discrete time implementations having switched capacitors have a dynamic range that is limited by thermal noise, require a large bandwidth for the reconstruction amplifier/low pass filter, and typically requires more area in a circuit due to the need for large charge transfer capacitors. Continuous time implementations generate distortion and in-band noise due to the unmatched rise/fall times and intersymbol interference, are very sensitive to clock jitter, and multi-bit truncation and noise filters can mitigate sensitivity.
Thus, there is a need for an efficient and accurate DAC that can overcome these and other problems with current DACs and drive a Class D amplifier.